Please refer to FIG. 1, a process flow diagram illustrating a conventional integrated circuit (IC) design and manufacture flow. The major steps involved in the conventional integrated circuit design includes: definition of system specification (step 11), architectural design (step 12), functional design and logic design (step 13), circuit design (step 14), and physical design (step 15). Data from the physical design stage should go through a series of physical verification steps and signoff checks (step 16) before they are taped-out. Then, wafer fabrication (step 17) according to the physical design for the integrated circuit is performed. Following the fabrication stage, the fabricated ICs are packaged and tested (step 18), and demand IC chip products are obtained at last.
As shown in FIG. 2, the physical design stage/step (step 15) of the conventional IC design of FIG. 1 mainly includes sub-steps of: partitioning (step 151), floorplanning (step 152), placement (step 153), clock tree synthesis (CTS) (step 154), signal routing (step 155), and timing closure (step 156). The clock tree synthesis (step 154) is performed for minimizing or limiting clock skew between timing paths in one chip within an acceptable range. However, with the development of the integrated circuit technology, the clock operation frequency is rapidly increasing, the conventional synchronization mechanism needs more and more active delay cells for achieving further more precise timing control. Therefore, there is a need of improving the synchronization within the chip in a much effective or controllable manner.